Metal oxide semiconductor field effect transistor (MOSFET) is one of the important devices for integrated circuits. As the trend of miniaturizing the integrated circuits, the fabrication of the MOSFET also meets various issues to miniaturize them. The typically issue that relates to hot carriers injection is overcame by the development of lightly doped drain (LDD) structure. However, when the transistor is scaled down to submicron range, the transistor suffers the hot electron problem again. It is because that the transistor has short channel length and high supply power. The electric field strength in the devices is increased, thus the energetic electrons will inject into the silicon-oxide interface and be trapped within the gate oxide. Wei has suggested a buried and graded LDD structure to improve the hot electron reliability as seen in the article "Buried and Graded/Buried LDD Structure for Improved Hot-Electron Reliability, Ching-Yeu Wei, IEEE Electron Device Lett., 1986".
Lo has proposed a method to suppress the hot carrier induced degradation. In this technique, gate oxide is grown in pure N.sub.2 O ambient at 950 degrees centigrade. It reports that the N.sub.2 O gate oxide has significantly enhanced hot carrier immunity. Further, under the Fowler-Nordheim injection stress, the devices show an enhanced degradation with decreasing channel length and increasing channel width. Please see "Dependence of Hot-Carrier Immunity on Channel Length and Channel Width in MOSFET's with N.sub.2 O-Grown Gate Oxides, G. Q. Lo, et al., IEEE, Electron Device Lett.,1992".
In addition, the requirement of the devices is that the devices exhibit high operation speed and low operation power. For deep sub-micron meter MOS devices, the self-aligned silicide (SALICIDE) contact, ultra-shallow source and drain junction are used for improving the operation speed and short channel effect as seen in reference "High Performance 0.15 .mu.m Single Gate Co Salicide CMOS, T. Yoshitomi et al., 1996, Symposium on VLSI Technology Digest of Technical papers". The conventional TiSi.sub.2 suffers a serious problem relating to the sheet resistance increase of the fine line. Thus, in the technology, the CoSi.sub.2, NiSi have been used for deep sub-micron high speed CMOS due to the low sheet resistance of fine silicide line. The MOSFETs have extension region to suppress the short channel effect and achieve the high speed operation.
Another issue is relating to the supply power of the devices. When the supply-voltage is reduced, the threshold voltage needs to be scaled down to achieve the desired circuit switching speed. IBM has proposed that CMOS employs non-uniform channel doping profiles and ultra-shallow source and drain extensions and halos, which can be referenced in "CMOS technology scaling 0.1 .mu.m and beyond, IBM semiconductor research and development center, Bijan , Davari, IEDM, 96-555, 1996". For the high performance case, the threshold voltage is scaled down less than the supply voltage in order to maintain a reasonable standby current.
Further, in order to achieve the purpose of the present invention, an anti-reflective coating technology is used to improve the resolution of lithography. This can reference to the article "CVD SiN.sub.x Anti-reflective Coating for Sub-0.5 .mu.m Lithography, T. P. Ong, 1995, Symposium on VLSI Technology Digist of Technical Papers". The SiN.sub.x material can provide excellent anti-reflective layer that meets the requirement of the advanced integrated circuits. This material also be utilized to fabricate SRAM as the bottom anti-reflective coating (BARC). In addition, the present invention uses an etchant suggested by Mitani to form a recess portion of silicon substrate. The etchant exhibits high selectivity to silicon oxide for etching, and low damage for silicon. Please see "Buried Source and Drain (BSD) Structure for Ultra-shallow Junction Using Selective Deposition of Highly Doped Amorphous Silicon, Y. Mitani, 1996, Symposium on VLSI Technology Digist of Technical Papers"."